Prototype before tape-out: putting SoC logic on an FPGA first

Once a chip design goes to the fab, a mistake costs months. Simulation catches a great deal, but simulations are slow and only as good as the test cases someone thought to write. An FPGA prototype closes part of that gap: the same RTL that will become silicon runs on a reprogrammable device, at a speed where real firmware and real peripherals can be attached.

The digital side of VAAYU was prototyped this way.

What a prototype is good for

• Firmware development can start early. The software team gets a working target long before silicon arrives.
• Long-running behaviour. Sleep and wake cycles that take hours of simulated time run in real time on a board.
• System integration. The prototype can talk to an actual receiver, so framing and timing are tested end to end.
• Demonstrations. A working board is easier to show to a partner than a waveform.

The flow

Step	What happens
RTL	The design is written in Verilog or VHDL
Synthesis	RTL is mapped to the FPGA's logic cells
Place and route	Cells are placed and wired on the device
Bitstream	A configuration file is generated and loaded
Bring-up	The design is exercised on the board with test equipment

What an FPGA does not tell you

An FPGA prototype is not the chip, and it helps to be clear about the differences.

• Analog and RF are not on the FPGA. Sensor front ends and radios have to be stood in for with discrete parts or models, and verified separately.
• Power numbers do not transfer. FPGA power consumption says little about the final silicon.
• Timing is different. A path that meets timing on the FPGA still has to be closed in the ASIC flow, and the reverse.
• Some constructs change. Clock gating and memories are usually implemented differently on the two targets, so those parts of the RTL need care.

Used with those limits in mind, the prototype answers the question simulation is worst at: does the whole system behave when it is left running?