About Entra
A chip company
from Dharwad
Entra Innovations is a semiconductor product startup incubated at IIT Dharwad's dhaRti Foundation. We are building VAAYU, India's indigenous TPMS system-on-chip.
Our story
Why we started, and why here
Entra began in 2025 with a plain observation. India is mandating tyre-pressure monitoring on new vehicles, yet the chips inside those systems are imported. The value, and the know-how, sit somewhere else.
We set out to design that chip in India. VAAYU brings sensing, a RISC-V controller and RF together on one die, built to AIS-154 and ready for export markets under UN ECE R141.
We are doing it from Dharwad, a tier-2 city in North Karnataka, on the permanent campus of IIT Dharwad. India's next generation of deep-tech companies will not all come from metros. We intend to be proof of that: a product company solving real problems, starting in India and going to the world.
Design standards-compliant chips in India that make Indian roads safer.
Become a leading Indian fabless company for automotive and networking silicon.
Indigenous by design
We design the digital, analog and RF ourselves, so the know-how stays in India.
Academic depth, industry pace
IIT Dharwad faculty and industry engineers work on the same bench.
Products, not services
We are a fully product-based company. What we design ships as our own chip.
Talent from where we are
We train and hire engineers in North Karnataka instead of waiting for them to leave.
Collaborations
Built with IIT Dharwad
Entra works with two research labs at IIT Dharwad and is incubated at the institute's dhaRti Foundation.
Research collaboration
iCAS Lab
IIT Dharwad
Integrated circuit design research at IIT Dharwad. We work with the lab on the circuits that go into VAAYU.
Research collaboration
FutureG Networks Lab
IIT Dharwad
Next-generation networks research at IIT Dharwad. We work with the lab on wireless and O-RAN systems.
Incubator
dhaRti Foundation
IIT Dharwad
The Dharwad Research & Technology Incubator of IIT Dharwad, where Entra Innovations is incubated.
National programme support
Proudly part of India's semiconductor growth story
VAAYU is being developed under the Chips to Startup (C2S) Programme of MeitY, Government of India.
Chips to Startup (C2S) Programme
The VAAYU TPMS SoC is being developed under the Chips to Startup (C2S) Programme of the Ministry of Electronics and Information Technology (MeitY). Our co-founder and CPO, Dr. Nagaveni S, is the Chief Investigator of the project.
Ministry of Electronics and Information Technology (MeitY) · Government of India
Milestones
The journey so far
2025
Founded
Entra Innovations LLP is incorporated by IIT Dharwad faculty and students, and incubated at the dhaRti Foundation.
2025
Chips to Startup (C2S) Programme
VAAYU development begins under MeitY's C2S Programme, Government of India.
2025–26
VAAYU design and FPGA prototype
Architecture, RTL, analog and RF design. Digital design prototyped on an FPGA.
Aug 2026
DIR-V Symposium, IIT Madras
The Entra and iCAS Lab team takes part in the Digital India RISC-V Symposium 2026.
Sep 2026
SEMICON India 2026
Entra pitches to investors at Startup Mitra, the event's investor pitch forum.
Oct 2026
Dr. M. J. Zarabi Indigenisation Award
Entra exhibits at India Mobile Congress 2026, where VAAYU wins the inaugural award.
Oct 2026
Emerging Technologies Hackathon 2026
First rank at the hackathon organised by TCOE India.
Next
Tape-out and engineering samples
First silicon and sample modules for evaluation partners.
Then
Validation and OEM pilots
Silicon validation, AIS-154 type-approval testing and vehicle integration pilots.
Out in the ecosystem
From the lab to the national stage
In 2026 we took VAAYU to the DIR-V Symposium, SEMICON India and India Mobile Congress.
Leadership
The people behind the chip
IIT Dharwad faculty and industry veterans, working together.
Ritesh Belgudri
Co-founder & Chief Executive Officer
More than a decade in FPGA design and applications engineering, working with developers and architects across industries. Leads Entra’s vision and strategy. PhD scholar under the Visvesvaraya PhD Scheme for Electronics and IT, a Government of India initiative by MeitY.
LinkedIn →
Dr. Koteswararao Kondepu
Co-founder & Chief Technology Officer
Associate Professor at IIT Dharwad. Ph.D. in Computer Science and Engineering from IMT Lucca, Italy. Works on hardware acceleration of RAN functions, Open RAN and AI/ML for networks.
LinkedIn →
Dr. Nagaveni S
Co-founder & Chief Product Officer
Assistant Professor at IIT Dharwad and Chief Investigator of the TPMS SoC development project under MeitY’s Chips to Startup (C2S) Programme. Ph.D. in Microelectronics and VLSI from IIT Hyderabad. Works on analog and mixed-signal circuits, AI/ML for analog design and SoC development.
LinkedIn →
Gurudev (Gary) Goud
Executive Vice President — Growth, GTM & Alliances
Leads growth, partnerships, alliances and go-to-market, building relationships with OEMs and key stakeholders.
LinkedIn →Want to build chips from Dharwad?
We are hiring engineers and welcome interns who want to work on real silicon.